View LTC2751_5038731.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC2751 Current Output 12-/14-/16-Bit SoftSpan DACs with Parallel I/O
TM
FEATURES
DESCRIPTION
The LTC(R)2751 is a family of 12-, 14-, and 16-bit multiplying parallel-input, current-output DACs. They operate from a single 2.7V to 5.5V supply. All parts are guaranteed monotonic over temperature. The LTC2751A-16 provides 16-bit performance (1LSB INL and DNL) over temperature without any adjustments. These SoftSpanTM DACs offer six output ranges--two unipolar and four bipolar--that can be programmed through the parallel interface, or pinstrapped for operation in a single range. These parts use a bidirectional input/output parallel interface that allows readback of any on-chip register. A power-on circuit resets the DAC output to 0V when power is initially applied. A logic low on the CLR pin asynchronously clears the DAC to 0V in any output range. The parts are specified over commercial and industrial temperature ranges.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Six Programmable Output Ranges Unipolar: 0V to 5V, 0V to 10V Bipolar: 5V, 10V, 2.5V, -2.5V to 7.5V Maximum 16-Bit INL Error: 1 LSB over Temperature Low 1A (Maximum) Supply Current Guaranteed Monotonic over Temperature Low Glitch Impulse 1nV * s 2.7V to 5.5V Single Supply Operation 2s Settling Time to 1 LSB Reference Input: 15V Parallel Interface with Readback of All Registers Asynchronous CLR Pin Clears DAC Output to 0V in Any Output Range Power-On Reset to 0V 38-Pin 5mm x 7mm QFN Package
APPLICATIONS

High Resolution Offset and Gain Adjustment Process Control and Industrial Automation Automatic Test Equipment Data Acquisition Systems
TYPICAL APPLICATION
16-Bit DAC with Software Selectable Ranges
REF 5V
LTC2751-16 Integral Nonlinearity
VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 0.4 1.0
-
1/2 LT(R)1469
+
2 RIN R1 1 RCOM R2
C2 150pF 38 37 36 REF ROFS RFB
INL (LSB)
0.2 0.0 -0.2 -0.4
C1 15pF
LTC2751-16 WR UPD READ D/S CLR 31 30 29 28 17 18 WR UPD READ D/S CLR MSPAN 3, 32, 33 SPAN I/O S2-S0 6-14, 19-25 DATA I/O D15-D0 3 16 RVOS 34 16-BIT DAC WITH SPAN SELECT IOUT2 4 GND VDD 16 15 C3 0.1F
+
5V
2751 TA01
-
1/2 LT1469 VOUT
IOUT1
35
-0.6 -0.8 -1.0 0 16384 32768 CODE 49152
25C 90C -45C 65535
2751 TA01b
2751f
1
LTC2751 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
IOUT1, IOUT2, RCOM to GND .....................................0.3V RFB, ROFS, RIN, REF, RVOS to GND ...........................15V VDD to GND .................................................. -0.3V to 7V S2, S1, S0, D15-D0, MSPAN, READ, D/S,WR, UPD, CLR to GND ........-0.3V to VDD + 0.3V (7V Max)
Operating Temperature Range LTC2751C .................................................... 0C to 70C LTC2751I ................................................. -40C to 85C Maximum Junction Temperature .......................... 125C Storage Temperature Range................... -65C to 150C
PIN CONFIGURATION
TOP VIEW IOUT1 RVOS ROFS ROFS REF REF RFB S1 S0 TOP VIEW IOUT1 RVOS ROFS REF RFB S1 S0 TOP VIEW IOUT1 RVOS RFB S1 S0 31 WR 30 UPD 29 READ 28 D/S 27 NC 39 26 NC 25 D0 24 D1 23 D2 22 D3 21 D4 20 D5 13 14 15 16 17 18 19 D8 D7 VDD GND CLR MSPAN D6 38 37 36 35 34 33 32 RCOM 1 RIN 2 S2 3 IOUT2 4 NC 5 D11 6 D10 7 D9 8 D8 9 D7 10 D6 11 D5 12 13 14 15 16 17 18 19 D4 D3 VDD GND CLR MSPAN D2 39 31 WR 30 UPD 29 READ 28 D/S 27 NC 26 NC 25 NC 24 NC 23 NC 22 NC 21 D0 20 D1 RCOM 1 RIN 2 S2 3 IOUT2 4 NC 5 D13 6 D12 7 D11 8 D10 9 D9 10 D8 11 D7 12 13 14 15 16 17 18 19 D6 D5 VDD GND CLR MSPAN D4 39 38 37 36 35 34 33 32 31 WR 30 UPD 29 READ 28 D/S 27 NC 26 NC 25 NC 24 NC 23 D0 22 D1 21 D2 20 D3 RCOM 1 RIN 2 S2 3 IOUT2 4 NC 5 D15 6 D14 7 D13 8 D12 9 D11 10 D10 11 D9 12 38 37 36 35 34 33 32
LTC2751-12 UHF PACKAGE 38-LEAD (5mm x 7mm) PLASTIC QFN
LTC2751-14 UHF PACKAGE 38-LEAD (5mm x 7mm) PLASTIC QFN
LTC2751-16 UHF PACKAGE 38-LEAD (5mm x 7mm) PLASTIC QFN
TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC2751CUHF-12#PBF LTC2751IUHF-12#PBF LTC2751CUHF-14#PBF LTC2751IUHF-14#PBF TAPE AND REEL LTC2751CUHF-12#TRPBF LTC2751IUHF-12#TRPBF LTC2751CUHF-14#TRPBF LTC2751IUHF-14#TRPBF PART MARKING* 275112 275112 275114 275114 275116 275116 275116 275116 PACKAGE DESCRIPTION 38-Lead (5mm x 7mm) Plastic QFN 38-Lead (5mm x 7mm) Plastic QFN 38-Lead (5mm x 7mm) Plastic QFN 38-Lead (5mm x 7mm) Plastic QFN 38-Lead (5mm x 7mm) Plastic QFN 38-Lead (5mm x 7mm) Plastic QFN 38-Lead (5mm x 7mm) Plastic QFN 38-Lead (5mm x 7mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C
LTC2751BCUHF-16#PBF LTC2751BCUHF-16#TRPBF LTC2751BIUHF-16#PBF LTC2751BIUHF-16#TRPBF LTC2751ACUHF-16#PBF LTC2751ACUHF-16#TRPBF LTC2751AIUHF-16#PBF LTC2751AIUHF-16#TRPBF
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2751f
2
LTC2751 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Static Performance Resolution Monotonicity DNL INL GE GETC BZE BZSTC PSR ILKG CIOUT1 Differential Nonlinearity Integral Nonlinearity Gain Error Gain Error Temperature Coefficient Bipolar Zero Error Bipolar Zero Temperature Coefficient Power Supply Rejection IOUT1 Leakage Current Output Capacitance VDD = 5V, 10% VDD = 3V, 10% TA = 25C TMIN to TMAX Full-Scale Zero Scale

VDD = 5V, VREF = 5V unless otherwise specified. The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
LTC2751-12 CONDITIONS MIN 12 12 1 1 0.5 0.6
LTC2751-14 MIN 14 14 1 1 1.5 0.6 5 TYP MAX
LTC2751B-16 MIN 16 16 1 2 20 0.6 3 0.5 12 TYP MAX
LTC2751A-16 MIN 16 16 0.2 0.4 4 0.6 2 0.5 8 1 1 14 TYP MAX UNITS Bits Bits LSB LSB LSB ppm/C LSB ppm/C LSB/V nA pF pF
TYP
MAX
All Output Ranges Gain/Temp All Bipolar Ranges
2
0.2 0.5
1
0.6 0.5
0.025 0.06 0.05 2 5 0.05 75 45
0.1 0.25 2 5 0.05 75 45
0.4 1 2 5
0.03 0.2 0.1 0.5 0.05 75 45 2 5
75 45
VDD = 5V, VREF = 5V unless otherwise specified. The denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL Resistances (Note 3) R1/R2 RREF RFB ROFS RVOS Reference Inverting Resistors DAC Input Resistance Feedback Resistor Bipolar Offset Resistor Offset Adjust Resistor Output Settling Time Glitch Impulse Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error THD Power Supply VDD IDD Supply Voltage Supply Current, VDD Digital Inputs = 0V or VDD

PARAMETER
CONDITIONS (Note 4) (Note 3) (Note 3)

MIN 16 8 8 16 800
TYP 20 10 10 20 1000 2 1 1 0.5 -110 13
MAX
UNITS k k k k k s nV*s nV*s mV dB nV/Hz
Dynamic Performance 0V to 10V Range, 10V Step. To 0.0015% FS (Note 5) (Note 6) (Note 7) 0V to 10V Range, VREF = 10V, 10kHz Sine Wave (Note 8) Multiplying (Note 9) at IOUT1 2.7 0.5
Total Harmonic Distortion Output Noise Voltage Density
5.5 1
V A
2751f
3
LTC2751 ELECTRICAL CHARACTERISTICS
SYMBOL Digital Inputs VIH VIL IIN CIN Digital Outputs VOH VOL IOH = 200A IOL = 200A

VDD = 5V, VREF = 5V unless otherwise specified. The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
PARAMETER Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Input Capacitance CONDITIONS 3.3V VDD 5.5V 2.7V VDD < 3.3V 4.5V < VDD 5.5V 2.7V VDD 4.5V VIN = GND to VDD VIN = 0V (Note 10)

MIN 2.4 2
TYP
MAX
UNITS V V
0.8 0.6 1 6 VDD - 0.4 0.4
V V A pF V V
TIMING CHARACTERISTICS
SYMBOL PARAMETER VDD = 4.5V to 5.5V Write and Update Timing t1 t2 t3 t4 t5 t6 t7 t8 t13 t14 t15 t17 t18 t19 t20 t22 t23 t24 CLR Timing t25 CLR Pulse Width Low I/O Valid to WR Rising Edge Set-Up I/O Valid to WR Rising Edge Hold WR Pulse Width UPD Pulse Width UPD Falling Edge to WR Falling Edge WR Rising Edge to UPD Rising Edge D/S Valid to WR Falling Edge Set-Up Time WR Rising Edge to D/S Valid Hold Time WR Rising Edge to READ Rising Edge READ Falling Edge to WR Falling Edge
VDD = 5V, VREF = 5V unless otherwise specified. The denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C.
CONDITIONS MIN TYP MAX UNITS

9 9 20 20 0 0 9 9 9 20 30 30 9 9 9 9 0 20 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
No Data Shoot-Through (Note 10)

Readback Timing
(Note 10) CL = 10pF CL = 10pF (Note 10) No Update No Update (Note 10) (Note 10) (Note 10)

READ Rising Edge to I/O Propagation Delay UPD Valid to I/O Propagation Delay D/S Valid to READ Rising Edge READ Rising Edge to UPD Rising Edge UPD Falling Edge to READ Falling Edge READ Falling Edge to UPD Rising Edge I/O Bus Hi-Z to READ Rising Edge READ Falling Edge to I/O Bus Active
2751f
4
LTC2751 TIMING CHARACTERISTICS
SYMBOL PARAMETER VDD = 2.7V to 3.3V Write and Update Timing t1 t2 t3 t4 t5 t6 t7 t8 t13 t14 t15 t17 t18 t19 t20 t22 t23 t24 CLR Timing t25 CLR Pulse Width Low
VDD = 5V, VREF = 5V unless otherwise specified. The denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C.
CONDITIONS MIN TYP MAX UNITS
I/O Valid to WR Rising Edge Set-Up I/O Valid to WR Rising Edge Hold WR Pulse Width UPD Pulse Width UPD Falling Edge to WR Falling Edge WR Rising Edge to UPD Rising Edge D/S Valid to WR Falling Edge Set-Up Time WR Rising Edge to D/S Valid Hold Time WR Rising Edge to Read Rising Edge Read Falling Edge to WR Falling Edge Read Rising Edge to I/O Propagation Delay UPD Valid to I/O Propagation Delay D/S Valid to Read Rising Edge Read Rising Edge to UPD Rising Edge UPD Falling Edge to Read Falling Edge READ Falling Edge to UPD Rising Edge I/O Bus Hi-Z to Read Rising Edge Read Falling Edge to I/O Bus Active (Note 10) CL = 10pF CL = 10pF (Note 10) No Update No Update (Note 10) (Note 10) (Note 10) No Data Shoot-Through (Note 10)

18 18 30 30 0 0 18 18 18 40 40 40 18 9 9 18 0 40 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Readback Timing

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: Because of the proprietary SoftSpan switching architecture, the measured resistance looking into each of the specified pins is constant for all output ranges if the IOUT1 and IOUT2 pins are held at ground. Note 4: R1 is measured from RIN to RCOM ; R2 is measured from REF to RCOM . Note 5: Using LT1469 with CFEEDBACK = 15pF. A 0.0015% settling time of 1.7s can be achieved by optimizing the time constant on an individual
basis. See Application Note 74, "Component and Measurement Advances Ensure 16-Bit DAC Settling Time." Note 6: Measured at the major carry transition, 0V to 5V range. Output amplifier: LT1469; CFB = 27pF. Note 7. Full-scale transition; REF = 0V. Note 8. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output amplifier = LT1469. Note 9. Calculation from Vn = 4kTRB, where k = 1.38E-23 J/K (Boltzmann constant), R = resistance (), T = temperature (K), and B = bandwidth (Hz). Note 10. Guaranteed by design. Not production tested.
2751f
5
LTC2751 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2751-16 Integral Nonlinearity (INL)
VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 - 0.8 -1.0 0 16384 32768 CODE 49152 65535
2751 G01
TA = 25C, unless otherwise noted.
Differential Nonlinearity (DNL)
VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2751 G02
1.0
1.0
INL vs Temperature
VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 0.4 INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 - 0.8 -1.0 -40 -20 20 40 0 60 TEMPERATURE (C) 80
2751 G04
DNL vs Temperature
VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 1.0 8
Bipolar Zero vs Temperature
VDD = 5V 6 VREF = 5V 10V RANGE 4
1.0
+INL DNL (LSB)
0.4 +DNL -DNL BZE (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -20 20 40 0 60 TEMPERATURE (C) 80
2751 G05
2 0 2 4 6 8 -40 -20
0.5ppm/C (TYP)
-INL
20 40 0 60 TEMPERATURE (C)
80
2751 G06
Gain Error vs Temperature
16 VDD = 5V 12 VREF = 5V 10V RANGE 8 INL (LSB) GE (LSB) 4 0 -4 -8 -12 -16 -40 -20 20 40 0 60 TEMPERATURE (C) 80
2751 G07
INL vs VREF
1.0 VDD = 5V 0.8 5V RANGE 0.6 0.4 INL (LSB) +INL +INL 1.0
DNL vs VREF
VDD = 5V 0.8 5V RANGE 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 +DNL -DNL +DNL -DNL
0.6ppm/C (TYP)
0.2 0.0 -0.2 -0.4 -0.6 -0.8
-INL
-INL
-1.0 -10 -8 -6
4
202 VREF (V)
4
6
8
10
-1.0 -10 -8 -6
4
2751 G08
202 VREF (V)
4
6
8
10
2751 G09
2751f
6
LTC2751 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2751-16 INL vs VDD
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 - 0.8 -1.0 2.5 3 3.5 4 4.5 VDD (V) 5 5.5
2751 G09b
TA = 25C, unless otherwise noted.
Settling 0V to 10V
UPD 5V/DIV +INL GATED SETTLING WAVEFORM 250V/DIV
2751 G10
-INL
500ns/DIV USING LT1469 AMP CFEEDBACK = 12pF 0V TO 10V STEP
LTC2751-14 Integral Nonlinearity (INL)
VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 0.4 DNL (LSB) 16383
2751 G11
Differential Nonlinearity (DNL)
VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 1.0
1.0
INL (LSB)
0.2 0.0 -0.2 -0.4 -0.6 - 0.8 -1.0 0 4096 8192 CODE 12288
0
4096
8192 CODE
12288
16383
2751 G12
LTC2751-12 Integral Nonlinearity (INL)
VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 - 0.8 -1.0 0 1024 2048 CODE 3072 4095
2751 G13
Differential Nonlinearity (DNL)
1.0 VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4095
2751 G14
1.0
2751f
7
LTC2751 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2751-12, LTC2751-14, LTC2751-16 Midscale Glitch
12 10 UPD 5V/DIV 8 IDD (mA) VDD = 5V 6 4
2751 G15
TA = 25C, unless otherwise noted.
Supply Current vs Logic Input Voltage
1nV*s (TYP)
VOUT 2mV/DIV
500ns/DIV USING AN LT1469 VDD = 5V CFEEDBACK = 27pF VREF = 5V 0V TO 5V RANGE
2 0 0 1
VDD = 3V 2 3 LOGIC VOLTAGE (V) 4
2751 G16
5
ALL DIGITAL PINS TIED TOGETHER (EXCEPT READ TIED TO GND)
Logic Threshold vs Supply Voltage
2 1.75 1.5 1.25 FALLING 1 0.75 0.5 0.1 2.5 3 3.5 4 4.5 VDD (V) 5 5.5
2751 G17
Supply Current vs Update Frequency
1000
RISING
SUPPLY CURRENT (A)
LOGIC THRESHOLD (V)
100
10
1 VDD = 5V VDD = 3V 10 100 10k 100k 1k UPD FREQUENCY (Hz) 1M
2751 G18
ALTERNATING ZERO-SCALE/FULL-SCALE (LTC2751-16)
2751f
8
LTC2751 PIN FUNCTIONS
RCOM (Pin 1): Center Tap Point of RIN and REF. Normally tied to the negative input of the external reference inverting amplifier. RIN (Pin 2): Input Resistor for External Reference Inverting Amplifier. Normally tied to the external reference voltage VREF and to ROFS (Pin 37). Typically 5V; accepts up to 15V. S2 (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC. IOUT2 (Pin 4): DAC Current Output Complement. Tie IOUT2 to GND. NC (Pin 5): No Connection. Must be tied to GND, provides necessary shielding for IOUT2. D3-D11 (Pins 6-14): LTC2751-12 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D11 is the MSB. D5-D13 (Pins 6-14): LTC2751-14 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D13 is the MSB. D7-D15 (Pins 6-14): LTC2751-16 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D15 is the MSB. VDD (Pin 15): Positive Supply Input 2.7V VDD 5.5V. Requires a 0.1F bypass capacitor to GND. GND (Pin 16): Ground. Tie to ground. CLR (Pin 17): Asynchronous Clear. When CLR is taken to a logic low, the data registers are reset to the zero-volt code for the present output range (VOUT = 0V). MSPAN (Pin 18): Manual Span Control Pin. MSPAN is used to configure the LTC2751 for operation in a single, fixed output range. When configured for single-span operation, the output range is set via hardware pin strapping. The span input and DAC registers are transparent and do not respond to write or update commands. To configure the part for single-span use, tie MSPAN directly to VDD . If MSPAN is instead connected to GND (SoftSpan configuration), the output ranges are set and verified by using write, update and read operations. See Manual Span Configuration in the Operation section. MSPAN must be connected either directly to GND (SoftSpan configuration) or VDD (single-span configuration). D0-D2 (Pins 19-21): LTC2751-12 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D0 is the LSB. D0-D4 (Pins 19-23): LTC2751-14 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D0 is the LSB. D0-D6 (Pins 19-25): LTC2751-16 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D0 is the LSB. NC (Pins 22-27): LTC2751-12 Only. No Connection. NC (Pins 24-27): LTC2751-14 Only. No Connection. NC (Pins 26, 27): LTC2751-16 Only. No Connection. D/S (Pin 28): Data/Span Select. This pin is used to select activation of the data or span I/O pins (D0 to D15 or S0 to S2, respectively), along with their respective dedicated registers, for write or read operations. Update operations ignore D/S, since all updates affect both data and span registers. For single-span operation, tie D/S to GND. READ (Pin 29): Read Pin. When READ is asserted high, the data I/O pins (D0-D15) or span I/O pins (S0-S2) output the contents of the selected register (see Table 1). For single-span operation, readback of the span I/O pins is disabled. UPD (Pin 30): Update and Buffer Select Pin. When READ is held low and UPD is asserted high, the contents of the input registers (both data and span) are copied into their respective DAC registers. The output of the DAC is updated, reflecting the new DAC register values. When READ is held high, the update function is disabled and the UPD pin functions as a buffer selector--logic low to select the input register, high for the DAC register. See Readback in the Operation section. WR (Pin 31): Active Low Write Pin. A Write operation copies the data present on the data or span I/O pins (D0D15 or S0-S2, respectively) into the input register. When READ is high, the Write function is disabled. S0 (Pin 32): Span I/O Bit 0. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC.
2751f
9
LTC2751 PIN FUNCTIONS
S1 (Pin 33): Span I/O Bit 1. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC. RVOS (Pin 34): DAC Offset Adjust. Nominal input range is 5V. If not used, RVOS should be shorted to IOUT2 . IOUT1 (Pin 35): DAC current output; normally tied to the negative input of the I/V converter amplifier. RFB (Pin 36): DAC Feedback Resistor; normally tied to the output of the I/V converter amplifier. The DAC output current from IOUT1 flows through the feedback resistor to the RFB pin. ROFS (Pin 37): Bipolar Offset Network. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to 15V; normally tied to the positive reference voltage at RIN (Pin 2). REF (Pin 38): Feedback Resistor for the Reference Inverting Amplifier, and Reference Input for the DAC. Normally tied to the output of the reference inverting amplifier. Typically -5V. Accepts up to 15V. Exposed Pad (Pin 39): Ground. The Exposed Pad must be soldered to the PCB.
2751f
10
LTC2751 BLOCK DIAGRAM
1 RCOM RIN 2 READ 29 WR 31 UPD 30 D/S 28 CLR 17 MSPAN 18 I/O PORT 3 3, 32, 33 SPAN I/O S2-S0 I/O PORT 16 6-14, 19-25 DATA I/O D15-D0
2751 BD
38 REF R2
37 ROFS
36 RFB IOUT1
R1
35 4
16-BIT DAC WITH SPAN SELECT
IOUT2
3
16
CONTROL LOGIC
DAC REGISTER 3
DAC REGISTER 16
INPUT REGISTER
INPUT REGISTER
2751f
11
LTC2751 TIMING DIAGRAMS
Write, Update and Clear Timing
t3 t1 WR t2
I/O INPUT t5 UPD t4 t8 t6
t7 D/S
t25 CLR
2751 TD01
Readback Timing
READ t13 WR t23 I/O INPUT t15 I/O OUTPUT t17 t20 t19 UPD t18 D/S
2751 TD02
t14
t24
t22
OPERATION
Output Ranges The LTC2751 is a current-output, parallel-input precision multiplying DAC with software-programmable output ranges. SoftSpan provides two unipolar output ranges (0V to 5V and 0V to 10V), and four bipolar ranges (2.5V, 5V, 10V and -2.5V to 7.5V). These ranges are obtained when an external precision 5V reference is used. When a reference voltage of 2V is used, the SoftSpan ranges become: 0V to 2V, 0V to 4V, 1V, 2V, 4V and -1V to 3V. The output ranges are linearly scaled for references other than 2V and 5V. Digital Section The LTC2751 family has four internal interface registers (see Block Diagram). Two of these--one input and one DAC register--are dedicated to the data I/O port, and two to the span I/O port. Each port is thus double-buffered. The double-buffered feature provides the capability to simultaneously update the span and code, which allows smooth voltage transitions when changing output ranges. It also permits the simultaneous updating of multiple DACs.
2751f
12
LTC2751 OPERATION
Write and Update Operations The data input register is loaded directly from a 16-bit microprocessor bus by holding the D/S pin low and then pulsing the WR pin low. The second register (DAC register) is loaded by pulsing the UPD pin high, which copies the data held in the input register into the DAC register. Note that updates always include both data and span; but the DAC register values will not change unless the input register values have been changed by writing. Loading the span input register is accomplished in a similar manner, by holding the D/S pin high and then bringing the WR pin low. The span and data register structures are the same except for the number of parallel bits--the span registers have three bits, while the data registers have 12, 14, or 16 bits. To make both registers transparent for flowthrough mode, tie WR low and UPD high. However, this defeats the deglitcher operation and output glitch impulse may increase. The deglitcher is activated on the rising edge of the UPD pin. The interface also allows the use of the input and DAC registers in a master-slave, or edge-triggered, configuration. This mode of operation occurs when WR and UPD are tied together and driven by a single clock signal. The data bits are loaded into the input register on the falling edge of the clock and then loaded into the DAC register on the rising edge. The separation of data and span for write and read operations makes it possible to control both data and span on one 16-bit wide data bus by allowing span pins S2 to S0 to share bus lines with the data LSBs (D2 to D0). Since no write or read operation includes both span and data, there cannot be a conflict. The asynchronous clear pin resets the LTC2751 to 0V (zero-, half- or quarter-scale code) in any output range. CLR resets both the input and DAC data registers, while leaving the span registers undisturbed. These devices also have a power-on reset. If configured for SoftSpan operation, the part initializes to zero scale in the 0V to 5V output range. If configured for single-span operation, the part initializes to the zero-volt code in the chosen output range.
2751 F01
Table 1 shows the functions of the LTC2751.
Table 1. Write, Update and Read Functions
READ D/S 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 WR UPD 0 0 1 1 0 0 1 1 X X X X 0 1 0 1 0 1 0 1 0 1 0 1 SPAN I/O Update DAC Register Write to Input Register Write/Update (Transparent) Update DAC register Read Input Register Read DAC Register DATA I/O Write to Input Register Write/Update (Transparent) Update DAC Register Update DAC Register Read Input Register Read DAC Register -
X = Don't Care
Manual Span Configuration Multiple output ranges are not needed in some applications. To configure the LTC2751 for single-span operation, tie the MSPAN pin to VDD and the D/S pin to GND. The desired output range is then specified by the span I/O pins (S0, S1 and S2) as usual, but the pins are programmed by tying directly to GND or VDD (see Figure 1 and Table 2). In this configuration, the part will initialize to the chosen output range at power-up, with VOUT = 0V. When configured for manual span operation, span pin readback is disabled.
VDD
MSPAN S2 S1 S0 D/S WR
VDD LTC2751-16
UPD
READ 16 DATA I/O
Figure 1. Configuring the LTC2751 for Single-Span Operation (10V Range)
2751f
13
LTC2751 OPERATION
Table 2. Span Codes
S2 0 0 0 0 1 1 S1 0 0 1 1 0 0 S0 0 1 0 1 0 1 SPAN Unipolar 0V to 5V Unipolar 0V to 10V Bipolar -5V to 5V Bipolar -10V to 10V Bipolar -2.5V to 2.5V Bipolar -2.5V to 7.5V
is a two-function pin. The update function is disabled when READ is high, and the UPD pin instead selects the input or DAC register for readback. Table 1 shows the readback functions for the LTC2751. The most common readback task is to check the contents of an input register after writing to it, before updating the new data to the DAC register. To do this, bring READ high while holding UPD low. The contents of the selected port's input register are output by the data or span I/O pins. To read back the contents of a DAC register, bring READ high, then bring UPD high. The contents of the selected data or span DAC register are output by the data or span I/O pins. Note: if no update is desired after the readback operation, UPD must be returned low before bringing READ low, otherwise the UPD pin will revert to its primary function and update the DAC. System Offset Adjustment Many systems require compensation for overall system offset. The RVOS offset adjustment pin is provided for this purpose. For noise immunity and ease of adjustment, the control voltage is attenuated to the DAC output: VOS = -0.01 * V(RVOS) [0V to 5V, 2.5V spans] VOS = -0.02 * V(RVOS) [0V to 10V, 5V, -2.5V to 7.5V spans] VOS = -0.04 * V(RVOS) [10V span] The nominal input range of this pin is 5V; other reference voltages of up to 15V may be used if needed. The RVOS pin has an input impedance of 1M. To preserve the settling performance of the LTC2751, this pin should be driven with a Thevenin-equivalent impedance of 10k or less. If not used, RVOS should be shorted to IOUT2.
Codes not shown are reserved and should not be used.
Readback The contents of any one of the four interface registers can be read back by using the READ pin in conjunction with the D/S and UPD pins. A readback operation is initiated by bringing READ to logic high. The I/O pins, which are high-impedance digital inputs when READ is low, selectively change to low-impedance logic outputs during readback. The I/O pins comprise two ports, data and span. The data I/O port consists of pins D0-D11, D0-D13 or D0-D15 (LTC2751-12, LTC2751-14 or LTC2751-16, respectively). The span I/O port consists of pins S0, S1 and S2 for all parts. Each I/O port has one dedicated input register and one dedicated DAC register. The register structure is shown in the Block Diagram. The D/S pin is used to select which I/O port (data or span) is configured to read back the contents of its registers. The unselected I/O port's pins remain high-impedance inputs. Once the I/O port is selected, its input or DAC register is selected for readback by using the UPD pin. Note that UPD
2751f
14
LTC2751 OPERATION--EXAMPLES
1. Load 5V range with the output at 0V. Note that since span and code are updated together, the output, if started at 0V, will stay there.
WR
SPAN I/O INPUT DATA I/O INPUT
010
8000 H
UPD UPDATE (5V RANGE, VOUT = 0V) D/S READ = LOW
2751 TD03
2. Load 10V range with the output at 5V, changing to -5V.
WR
SPAN I/O INPUT DATA I/O INPUT
011
C000 H
4000 H
UPD
UPDATE (5V)
UPDATE (-5V)
D/S READ = LOW
2751 TD04
3. Write and update midscale code in 0V to 5V range (VOUT = 2.5V) using readback to check the contents of the input and DAC registers before updating.
WR
DATA I/O INPUT DATA I/O HI-Z OUTPUT
8000 H
HI-Z
8000 H INPUT REGISTER
0000 H DAC REGISTER
UPD UPDATE (2.5V) D/S
READ
2751 TD05
2751f
15
LTC2751 APPLICATIONS INFORMATION
Op Amp Selection Because of the extremely high accuracy of the 16-bit LTC2751-16, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables 3 and 4 contain equations for evaluating the effects of op amp parameters on the LTC2751's accuracy when
Table 3. Variables for Each Output Range That Adjust the Equations in Table 4
OUTPUT RANGE 5V 10V 5V 10V 2.5V -2.5V to 7.5V A1 1.1 2.2 2 4 1 1.9 A2 2 3 2 4 1 3 A3 1 0.5 1 0.83 1.4 0.7 1 1 1 0.5 A4 A5 1 1.5 1.5 2.5 1 1.5
programmed in a unipolar or bipolar output range. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. Tables 3 and 4 can also be used to determine the effects of op amp parameters on the LTC2751-14 and the LTC2751-12. However, the results obtained from Tables 3 and 4 are in 16-bit LSBs. Divide these results by 4 (LTC2751-14) and 16 (LTC2751-12) to obtain the correct LSB sizing. Table 5 contains a partial list of LTC precision op amps recommended for use with the LTC2751. The easy-to-use design equations simplify the selection of op amps to meet the system's specified error budget. Select the amplifier from Table 5 and insert the specified op amp parameters in Table 4. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the part. Arithmetic summation gives an (unlikely) worst-case effect. A root-sum-square (RMS) summation produces a more realistic estimate.
Table 4. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1 Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.
OP AMP VOS1 (mV) INL (LSB) DNL (LSB) UNIPOLAR OFFSET (LSB) BIPOLAR ZERO ERROR (LSB) 5V A3 * VOS1 * 19.8 * V REF 5V IB1 * 0.13 * V REF 0 A4 * VOS2 * 13.1 *
B2
5V 5V 5V VOS1 * 0.82 * V A3 * VOS1 * 13.2 * V VOS1 * 3.2 * V REF REF REF 5V 5V 5V IB1 (nA) IB1 * 0.0003 * V IB1 * 0.00008 * V IB1 * 0.13 * V REF REF REF 16.5k 1.5k AVOL1 (V/V) A1 * A A2 * A 0 VOL1 VOL1 VOS2 (mV) IB2 (mV) AVOL2 (V/V) 0 0 0 0 0 0 0 0 0
() () ()
() () ()
() ()
() ()
REF
(V5V ) ) 5V A4 * (I * 0.13 * ( V )) A4 * ( 66k ) A
REF VOL2
(
UNIPOLAR GAIN ERROR (LSB) 5V VOS1 * 13.2 * V REF 5V IB1 * 0.0018 * V REF 131k A5 * AVOL1 5V VOS2 * 26.2 * VREF 5V IB2 * 0.26 * VREF 131k AVOL2
() () () () () ()
BIPOLAR GAIN ERROR (LSB) 5V VOS1 * 13.2 * V REF 5V IB1 * 0.0018 * V REF 131k A5 * AVOL1 5V VOS2 * 26.2 * VREF 5V IB2 * 0.26 * VREF 131k AVOL2
() () () () () ()
Table 5. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2751 with Relevant Specifications
AMPLIFIER SPECIFICATIONS VOS V 25 50 60 70 75 125 IB nA 2 0.35 0.25 20 10 10 A VOL V/mV 800 1000 1500 4000 5000 2000 VOLTAGE NOISE nV/Hz 10 14 14 2.7 5 5 CURRENT NOISE pA/Hz 0.12 0.008 0.008 0.3 0.6 0.6 SLEW RATE V/s 0.25 0.2 0.16 4.5 22 22 GAIN BANDWIDTH PRODUCT MHz 0.8 0.7 0.75 12.5 90 90 tSETTLING with LTC2751 s 120 120 115 19 2 2 POWER DISSIPATION mW 46 11 10.5/Op Amp 69/Op Amp 117 123/Op Amp
2751f
AMPLIFIER LT1001 LT1097 LT1112 (Dual) LT1124 (Dual) LT1468 LT1469 (Dual)
16
LTC2751 APPLICATIONS INFORMATION
Op amp offset will contribute mostly to output offset and gain error and has minimal effect on INL and DNL. For the LTC2751-16, a 250V op amp offset will cause about 0.8LSB INL degradation and 0.2LSB DNL degradation with a 5V reference. For the LTC2751 programmed in 5V unipolar mode, the same 250V op amp offset will cause a 3.3LSB zero-scale error and a 3.3LSB gain error. While not directly addressed by the simple equations in Tables 3 and 4, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp's data sheet to find the worst-case VOS and IB over temperature. Then, plug these numbers in the VOS and IB equations from Table 4 and calculate the temperature-induced effects. For applications where fast settling time is important, Application Note 74, "Component and Measurement Advances Ensure 16-Bit DAC Settling Time," offers a thorough discussion of 16-bit DAC settling time and op amp selection. Precision Voltage Reference Considerations Much in the same way selecting an operational amplifier for use with the LTC2751 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC2751 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 16-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference with low output voltage initial tolerance, like the LT1236 (0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference's output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit's INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. As precision DAC applications move to 16-bit and higher performance, reference output voltage noise may contribute a dominant share of the system's noise floor. This in turn can degrade system dynamic range and signal-tonoise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references, like the LT1236, produce low output noise in the 0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V or 10V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise.
Table 6. Partial List of LTC Precision References Recommended for Use with the LTC2751 with Relevant Specifications
REFERENCE LT1019A-5, LT1019A-10 LT1236A-5, LT1236A-10 LT1460A-5, LT1460A-10 LT1790A-2.5 INITIAL TOLERANCE 0.05% 0.05% 0.075% 0.05% TEMPERATURE DRIFT 5ppm/C 5ppm/C 10ppm/C 10ppm/C 0.1Hz to 10Hz NOISE 12VP-P 3VP-P 20VP-P 12VP-P
Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding techniques should be used. IOUT2 must be tied to the star ground with as low a resistance as possible. When it is not possible to locate star ground close to IOUT2, a low resistance trace should be used to route this pin to star ground. This minimizes the voltage drop from this pin to ground caused by the code dependent current flowing to ground. When the resistance of this circuit board trace becomes greater than 1, a force/sense amplified configuration should be used to drive this pin (see Figure 2). This preserves the excellent accuracy (1LSB INL and DNL) of the LTC2751-16.
2751f
17
LTC2751 APPLICATIONS INFORMATION
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE IOUT2 6 200 200 1000pF
2
6 1 ZETEX BAT54S 2 REF 5V 3
LT1468 3
IOUT2 1 5
6
LT1001 3
-
1/2 LT(R)1469
ZETEX* BAT54S 7 C2** 150pF 38 R2 2 3
6
+
*SCHOTTKY BARRIER DIODE 37 36 REF ROFS RFB
2 RIN R1
1 RCOM
C1 15pF 15V 0.1 F 8
LTC2751-16 WR UPD READ D/S CLR 31 30 29 28 17 18 IOUT1 WR UPD READ D/S CLR MSPAN 3, 33, 32 SPAN I/O S2-S0 6-14, 19-25 DATA I/O D15-D0 3 16 RVOS 34 16-BIT DAC WITH SPAN SELECT IOUT2 4 GND VDD 16 15 3 35 2
5V C3 0.1 F
**FOR MULTIPLYING APPLICATIONS C2 = 15pF
Figure 2. Basic Connections for SoftSpan VOUT DAC with Two Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifier
TYPICAL APPLICATIONS
16-Bit DAC with Software-Selectable Ranges
REF 5V 5
-
1/2 LT1469 7 C2** 150pF 38 R2 37 36 REF ROFS RFB
6
+
2 RIN R1
1 RCOM
C1 15pF 15V 8 0.1 F
LTC2751-16 WR UPD READ D/S CLR 31 30 29 28 17 18 WR UPD READ D/S CLR MSPAN 3, 33, 32 SPAN I/O S2-S0 6-14, 19-25 DATA I/O D15-D0 3 16 RVOS 34 16-BIT DAC WITH SPAN SELECT IOUT2 4 GND VDD 16 15 C3 0.1 F 3
**FOR MULTIPLYING APPLICATIONS C2 = 15pF
18
+
-
IOUT1
35
2
1/2 LT1469 4 -15V 0.1 F 5V
+
-
- +
- +
2
1/2 LT1469 0.1 F
1
VOUT
4 -15V
2751 F02
1
VOUT
2751 TA02
2751f
LTC2751 PACKAGE DESCRIPTION
UHF Package 38-Lead Plastic QFN (5mm x 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 0.05
5.50 0.05 (2 SIDES) 4.10 0.05 (2 SIDES) 3.15 0.05 (2 SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC 5.15 0.05 (2 SIDES) 6.10 0.05 (2 SIDES) 7.50 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (2 SIDES) 0.75 0.05 0.00 - 0.05 3.15 0.10 (2 SIDES) PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 37 38 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2
7.00 0.10 (2 SIDES)
5.15 0.10 (2 SIDES)
0.40 0.10 0.200 REF 0.25 0.05 0.75 0.05 0.200 REF 0.00 - 0.05 0.50 BSC R = 0.115 TYP
(UH) QFN 0205
BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
2751f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2751 TYPICAL APPLICATION
Offset and Gain Trim Circuits. Powering VDD from LT1027 Ensures Quiet Supply
V+ 2 C20 10 F IN U3 OUT 6 LT1027 TRIM 5 GND 4 2 R2 10k GND C23 0.1 F GND GND 15 6 7 8 9 10 11 12 13 14 19 20 21 22 23 24 25 D15 VDD D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 2 1 38 REF C22 0.001 F C13 10 F 2 8 V+ 1 2 R1 10k 1
- +
3
1
3 GND
U2A LT(R)1469 4 V-
37
36
C1 30pF
RIN RCOM
ROFS RFB
IOUT1
U1 LTC2751-16
DATA I/O
RVOS
34 GND
SPAN I/O
3 S2 33 S1 32 S0
D/S READ UPD 28 29 30
WR 31 WR
CLR 17 CLR
MSPAN NC 18 5
GND GND 16 39
2751 TA03
D/S READ UPD
GND
RELATED PARTS
PART NUMBER LT1027 LT1236A-5 LT1468 LT1469 DESCRIPTION Precision Reference Precision Reference 16-Bit Accurate Op-Amp Dual 16-Bit Accurate Op-Amp COMMENTS 1ppm/C Maximum Drift 0.05% Maximum Tolerance, 1ppm 0.1Hz to 10Hz Noise 90MHz GBW, 22V/s Slew Rate 90MHz GBW, 22V/s Slew Rate Software-Selectable (SoftSpan) Ranges, 1LSB INL, DNL, 16-Lead SSOP Package Integrated 4-Quadrant Resistors 1LSB INL, DNL, 0V to 10V, 0V to -10V, 10V Output Ranges Single DACs, SPI-Compatible, Single Supply, 0V to 5V Outputs in 3mm x 3mm DFN-10 Package Single DACs, I2C-Compatible, Single Supply, 0V to 5V Outputs in 3mm x 3mm DFN-10 Package 2LSB INL, 1LSB DNL, 1s Settling, Tiny MSOP-10, 3mm x 3mm DFN-10 Packages Software-Selectable (SoftSpan) Ranges, Integrated Amplifiers
2751f
LTC1588/LTC1589/ Serial 12-/14-/16-Bit IOUT Single DACs LTC1592 LTC1591/LTC1597 LTC1821 Parallel 14-/16-Bit IOUT Single DAC Parallel 16-Bit VOUT Single DAC
LTC2601/LTC2611/ Serial 12-/14-/16-Bit VOUT Single DACs LTC2621 LTC2606/LTC2616/ Serial 12-/14-/16-Bit VOUT Single DACs LTC2626 LTC2641/LTC2642 LTC2704 Serial 12-/14-/16-Bit Unbuffered VOUT Single DACs Serial 12-/14-/16-Bit VOUT Quad DACs
20 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2007
+
LT 0907 * PRINTED IN USA
IOUT2
4
5
-
U2B LT1469 7 VOUT
35
6

▲Up To Search▲

Price & Availability of LTC2751

	To Download LTC2751 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .